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A '''frequency divider''', also called a '''clock divider''' or '''scaler''' or '''prescaler''', is a [[Electronic circuit|circuit]] that takes an input signal of a [[frequency]], <math>f_{in}</math>, and generates an output signal of a frequency: | |||
:<math> | |||
f_{out} = \frac{f_{in}}{n} | |||
</math> | |||
where <math>n</math> is an integer. [[Phase-locked loop]] [[frequency synthesizer]]s make use of frequency dividers to generate a frequency that is a multiple of a reference frequency. Frequency dividers can be implemented for both [[analog electronics|analog]] and [[Digital data|digital]] applications. | |||
== Analog dividers == | |||
Analog frequency dividers are less common and used only at very high frequencies. Digital dividers implemented in modern IC technologies can work up to tens of GHz.{{citation needed|date=April 2012}} | |||
===Regenerative frequency divider=== | |||
A regenerative frequency divider, also known as a [[Miller frequency divider]],<ref>{{cite journal|author=R. L. Miller|title=Fractional Frequency Generators Utilizing Regenerative Modulation|journal=Proceedings of the IRE|year=1939|pages=446–457|doi=10.1109/JRPROC.1939.228513|volume=27|issue=7}} | |||
</ref> mixes the input signal with the feedback signal from the mixer. | |||
[[File:RFD block digram.jpg|center|Regenerative frequency divider]] | |||
The feedback signal is <math>f_{in}/2</math>. This produces sum and difference frequencies <math>f_{in}/2</math>, <math>3f_{in}/2</math> at the output of the mixer. A low pass filter removes the higher frequency and the <math>f_{in}/2</math> frequency is amplified and fed back into mixer. | |||
===Injection-locked frequency divider=== | |||
A free-running [[oscillator]] which has a small amount of a higher-frequency signal fed to it will tend to oscillate in step with the input signal. Such frequency dividers were essential in the development of [[television]]. | |||
It operates similarly to an [[injection locked oscillator]]. In an injection locked frequency divider, the frequency of the input signal is a multiple (or fraction) of the free-running frequency of the oscillator. While these frequency dividers tend to be lower power than broadband static (or flip-flop based) frequency dividers, the drawback is their low locking range. The ILFD locking range is inversely proportional to the quality factor (Q) of the oscillator tank. In integrated circuit designs, this makes an ILFD sensitive to process variations. Care must be taken to ensure the tuning range of the driving circuit (for example, a voltage-controlled oscillator) must fall within the input locking range of the ILFD. | |||
== Digital dividers == | |||
[[File:Frequency divider animation.gif|thumb|250px|An animation of a frequency divider implemented with D flip-flops, counting from 0 to 7 in binary]] | |||
For power-of-2 integer division, a simple binary counter can be used, clocked by the input signal. The least-significant output bit alternates at 1/2 the rate of the input clock, the next bit at 1/4 the rate, the third bit at 1/8 the rate, etc. An arrangement of [[Flip-flop (electronics)|flipflops]] are a classic method for integer-n division. Such division is frequency and phase coherent to the source over environmental variations including temperature. The easiest configuration is a series where each flip-flop is a divide-by-2. For a series of three of these, such system would be a divide-by-8. By adding additional logic gates to the chain of flip flops, other division ratios can be obtained. Integrated circuit logic families can provide a single chip solution for some common division ratios. | |||
Another popular circuit to divide a digital signal by an even integer multiple is a [[Johnson counter]]. This is a type of [[shift register]] network that is clocked by the input signal. The last register's complemented output is fed back to the first register's input. The output signal is derived from one or more of the register outputs. For example, a divide-by-6 divider can be constructed with a 3-register Johnson counter. The three valid values for each register are 000, 100, 110, 111, 011, and 001. This pattern repeats each time the network is clocked by the input signal. The output of each register is a f/6 square wave with 60° of phase shift between registers. Additional registers can be added to provide additional integer divisors. | |||
===Mixed signal division=== | |||
(''Classification:'' ''[[Asynchronous circuit|asynchronous]] [[sequential logic]]'')<br> | |||
An arrangement of [[D flip-flops]] are a classic method for integer-n division. Such division is frequency and phase coherent to the source over environmental variations including temperature. The easiest configuration is a series where each D flip-flop is a divide-by-2. For a series of three of these, such system would be a divide-by-8. More complicated configurations have been found that generate odd factors such as a divide-by-5. Standard, classic logic chips that implement this or similar frequency division functions include the 7456, 7457, 74292, and 74294. (see [[List of 7400 series integrated circuits]]) | |||
== Fractional-n dividers == | |||
{{Main|Dual-modulus prescaler}} | |||
A fractional-n frequency synthesizer can be constructed using two integer dividers, a divide-by-n and a divide-by-(n + 1) frequency divider. With a modulus controller, n is toggled between the two values so that the [[voltage-controlled oscillator|VCO]] alternates between one locked frequency and the other. The VCO stabilizes at a frequency that is the time average of the two locked frequencies. By varying the percentage of time the frequency divider spends at the two divider values, the frequency of the locked VCO can be selected with very fine granularity. | |||
=== Delta-sigma fractional-n synthesizers === | |||
If the sequence of divide by n and divide by (n + 1) is periodic, spurious signals appear at the VCO output in addition to the desired frequency. Delta-sigma fractional-n dividers overcome this problem by randomizing the selection of n and (n + 1), while maintaining the time-averaged ratios. | |||
==See also== | |||
{{Portal|Electronics}} | |||
*[[Phase-locked loop]] | |||
*[[Prescaler]] | |||
*[[Pulse-swallowing counter]] and [[pulse-swallowing divider]] | |||
==References== | |||
<references/> | |||
==External links== | |||
* [http://www.electronicproducts.com/ShowPage.asp?SECTION=3700&PRIMID=&FileName=FEBCON1.FEB2001 Delta-sigma fractional-n synthesizers] | |||
* [http://www.ece.uci.edu/~payam/RFD_ISCAS2005.pdf A Study of High Frequency Regenerative Frequency Dividers] | |||
[[Category:Electronic circuits]] | |||
Revision as of 22:29, 29 January 2014
A frequency divider, also called a clock divider or scaler or prescaler, is a circuit that takes an input signal of a frequency, , and generates an output signal of a frequency:
where is an integer. Phase-locked loop frequency synthesizers make use of frequency dividers to generate a frequency that is a multiple of a reference frequency. Frequency dividers can be implemented for both analog and digital applications.
Analog dividers
Analog frequency dividers are less common and used only at very high frequencies. Digital dividers implemented in modern IC technologies can work up to tens of GHz.Potter or Ceramic Artist Truman Bedell from Rexton, has interests which include ceramics, best property developers in singapore developers in singapore and scrabble. Was especially enthused after visiting Alejandro de Humboldt National Park.
Regenerative frequency divider
A regenerative frequency divider, also known as a Miller frequency divider,[1] mixes the input signal with the feedback signal from the mixer.
The feedback signal is . This produces sum and difference frequencies , at the output of the mixer. A low pass filter removes the higher frequency and the frequency is amplified and fed back into mixer.
Injection-locked frequency divider
A free-running oscillator which has a small amount of a higher-frequency signal fed to it will tend to oscillate in step with the input signal. Such frequency dividers were essential in the development of television.
It operates similarly to an injection locked oscillator. In an injection locked frequency divider, the frequency of the input signal is a multiple (or fraction) of the free-running frequency of the oscillator. While these frequency dividers tend to be lower power than broadband static (or flip-flop based) frequency dividers, the drawback is their low locking range. The ILFD locking range is inversely proportional to the quality factor (Q) of the oscillator tank. In integrated circuit designs, this makes an ILFD sensitive to process variations. Care must be taken to ensure the tuning range of the driving circuit (for example, a voltage-controlled oscillator) must fall within the input locking range of the ILFD.
Digital dividers
For power-of-2 integer division, a simple binary counter can be used, clocked by the input signal. The least-significant output bit alternates at 1/2 the rate of the input clock, the next bit at 1/4 the rate, the third bit at 1/8 the rate, etc. An arrangement of flipflops are a classic method for integer-n division. Such division is frequency and phase coherent to the source over environmental variations including temperature. The easiest configuration is a series where each flip-flop is a divide-by-2. For a series of three of these, such system would be a divide-by-8. By adding additional logic gates to the chain of flip flops, other division ratios can be obtained. Integrated circuit logic families can provide a single chip solution for some common division ratios.
Another popular circuit to divide a digital signal by an even integer multiple is a Johnson counter. This is a type of shift register network that is clocked by the input signal. The last register's complemented output is fed back to the first register's input. The output signal is derived from one or more of the register outputs. For example, a divide-by-6 divider can be constructed with a 3-register Johnson counter. The three valid values for each register are 000, 100, 110, 111, 011, and 001. This pattern repeats each time the network is clocked by the input signal. The output of each register is a f/6 square wave with 60° of phase shift between registers. Additional registers can be added to provide additional integer divisors.
Mixed signal division
(Classification: asynchronous sequential logic)
An arrangement of D flip-flops are a classic method for integer-n division. Such division is frequency and phase coherent to the source over environmental variations including temperature. The easiest configuration is a series where each D flip-flop is a divide-by-2. For a series of three of these, such system would be a divide-by-8. More complicated configurations have been found that generate odd factors such as a divide-by-5. Standard, classic logic chips that implement this or similar frequency division functions include the 7456, 7457, 74292, and 74294. (see List of 7400 series integrated circuits)
Fractional-n dividers
Mining Engineer (Excluding Oil ) Truman from Alma, loves to spend time knotting, largest property developers in singapore developers in singapore and stamp collecting. Recently had a family visit to Urnes Stave Church. A fractional-n frequency synthesizer can be constructed using two integer dividers, a divide-by-n and a divide-by-(n + 1) frequency divider. With a modulus controller, n is toggled between the two values so that the VCO alternates between one locked frequency and the other. The VCO stabilizes at a frequency that is the time average of the two locked frequencies. By varying the percentage of time the frequency divider spends at the two divider values, the frequency of the locked VCO can be selected with very fine granularity.
Delta-sigma fractional-n synthesizers
If the sequence of divide by n and divide by (n + 1) is periodic, spurious signals appear at the VCO output in addition to the desired frequency. Delta-sigma fractional-n dividers overcome this problem by randomizing the selection of n and (n + 1), while maintaining the time-averaged ratios.
See also
Sportspersons Hyslop from Nicolet, usually spends time with pastimes for example martial arts, property developers condominium in singapore singapore and hot rods. Maintains a trip site and has lots to write about after touring Gulf of Porto: Calanche of Piana.
References
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