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| [[File:Hindu lattice 2.svg|thumb |basic principle known from manual multiplication]]
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| <!-- [[File:And.svg|thumb | AND gate]]
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| [[File:Binary tree.svg|thumb | Would be used in reverse order]] -->
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| [[File:dadda tree 8x8.svg|thumb | Example of Dadda reduction on 8x8 multiplier]]
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| [[File:Full-adder.svg|thumb | Full adder, would in this case use only exclusive OR (XOR)]]
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| The '''Dadda multiplier''' is a hardware multiplier design invented by computer scientist [[Luigi Dadda]] in 1965. It is similar to the [[Wallace multiplier]], but it is slightly faster (for all operand sizes) and requires fewer gates (for all but the smallest operand sizes).[http://www.cerc.utexas.edu/~whitney/pdfs/spie03.pdf]
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| In fact, Dadda and Wallace multipliers have the same three steps:
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| # Multiply ([[Logical conjunction|logical AND]]) each bit of one of the arguments, by each bit of the other, yielding <math>n^2</math> results. Depending on position of the multiplied bits, the wires carry different weights, for example wire of bit carrying result of <math>a_2 b_3</math> is 32.
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| # Reduce the number of partial products to two layers of full and half adders.
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| # Group the wires in two numbers, and add them with a conventional [[adder (electronics)|adder]].
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| However, unlike Wallace multipliers that reduce as much as possible on each layer, Dadda multipliers do as few reductions as possible. Because of this, Dadda multipliers have a less expensive reduction phase, but the numbers may be a few bits longer, thus requiring slightly bigger adders.
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| To achieve this, the structure of the second step is governed by slightly more complex rules than in the Wallace tree. As in the Wallace tree, a new layer is added if any weight is carried by three or more wires. The reduction rules for the Dadda tree, however, are as follows:
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| * Take any three wires with the same weights and input them into a [[full adder]]. The result will be an output wire of the same weight and an output wire with a higher weight for each three input wires.
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| * If there are two wires of the same weight left, and the current number of output wires with that weight is equal to 2 (modulo 3), input them into a [[half adder]]. Otherwise, pass them through to the next layer.
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| * If there is just one wire left, connect it to the next layer.
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| This step does only as many adds as necessary, so that the number of output weights stays close to a multiple of 3, which is the ideal number of weights when using full adders as [[Adder (electronics)#3:2 compressors|3:2 compressors]].
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| However, when a layer carries at most three input wires for any weight, that layer will be the last one. In this case, the Dadda tree will use half adder more aggressively (but still not as much as in a Wallace multiplier), to ensure that there are only two outputs for any weight. Then, the second rule above changes as follows:
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| * If there are two wires of the same weight left, and the current number of output wires with that weight is equal to 1 or 2 (modulo 3), input them into a half adder. Otherwise, pass them through to the next layer.
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| == Algorithm example ==
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| This section explains the Dadda dot-diagram reduction example
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| * Let d<sub>1</sub> = 2 and d<sub>j+1</sub> = floor(3*d<sub>j</sub>/2)
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| ** This generates the sequence: d<sub>1</sub>=2, d<sub>2</sub>=3, d<sub>3</sub>=4, d<sub>4</sub>=6, d<sub>5</sub>=9, d<sub>6</sub>=13, ...
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| * Find the largest d<sub>j</sub> that is less than the maximum number of bits in any column.
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| ** For our example to the right, this would be 6
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| * For every column, use [[full adder]]s (FA) and [[half adder]]s (HA) to ensure that the number of elements in each column will be ≤ d<sub>j</sub>
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| ** When doing this, keep in mind that any column n that has an adder within it, will pass its sum bit to the next stage in column n and the carry bit to the n+1 column. The n+1 column will need to take this into account when determining the number of adders to use.
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| ; First bank
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| : Columns 0-5 don't need any adders, since they all have ≤ 6 bits
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| : Column 6 needs 1 HA (7 > 6) which reduces it to 6 bits and passes one carry bit to column 7.
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| : Column 7 can use a FA since it has 8 bits which would reduce the column to 6 bits, but since column 6 is passing in a carry bit, it needs one more HA to bring the total to 6 bits
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| : Column 8 needs a FA and a HA since it's getting 2 carry bits from column 7's adders.
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| : Column 9 only needs one FA
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| : Columns 10-14 do not need any adders since any carry bits from the previous columns don't result in a total greater than 6.
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| ; Second bank
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| : The next bank's d<sub>j</sub> = 4
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| : Columns 0-3 don't need any adders since they have ≤ 4 bits
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| : Column 4 needs a HA, (5 > 4)
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| : Column 5 needs a FA and a HA due to the carry bit
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| : Columns 6-10 need two FA since they all have 2 carry bits coming from the previous stage
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| : Column 11 only needs 1 FA to get to 4 bits after the carry bits come in
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| : Columns 12-14 don't need any adders since they all have < 4 bits
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| ; 3rd bank
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| : The next bank's d<sub>j</sub> = 3
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| : Columns 0-2 don't need any adders since they have ≤ 3 bits
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| : Column 3 only needs one HA to get to 3 bits
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| : Column 4-12 need a FA since they all have one carry-in bit coming in from the previous column
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| : Columns 13-14 don't need any adders since they have < 3 bits
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| ; 4th bank
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| : The next bank's d<sub>j</sub> = 2
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| : Columns 0-1 don't need any adders since they have ≤ 2 bits
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| : Column 2 only needs one HA to get to 2 bits
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| : Column 3-13 need a FA since they all have one carry-in bit coming in from the previous column
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| : Column 14 doesn't need an adder (1 < 2)
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| ; 5th bank
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| : At this point, everything is reduced to two bits and the resultant can be calculated from a 14 bit adder.
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| == Example ==
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| <math>n=4</math>, multiplying <math>a_3a_2a_1a_0</math> by <math>b_3b_2b_1b_0</math>: | |
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| # Reduction layer 1:
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| #* Pass the only weight-1 wire through, output: 1 weight-1 wire
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| #* Pass the two weight-2 wires through, outputs: 2 weight-2 wires
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| #* Add a full adder for weight 4, outputs: 1 weight-4 wire, 1 weight-8 wire
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| #* Add a full adder for weight 8, and pass the remaining wire through, outputs: 2 weight-8 wires, 1 weight-16 wire
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| #* Add a full adder for weight 16, outputs: 1 weight-16 wire, 1 weight-32 wire
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| #* Pass the two weight-32 wires through, outputs: 2 weight-32 wires
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| #* Pass the only weight-64 wire through, output: 1 weight-64 wire
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| # Wires at the output of reduction layer 1:
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| #* weight 1 - 1
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| #* weight 2 - 2
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| #* weight 4 - 1
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| #* weight 8 - 3
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| #* weight 16 - 2
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| #* weight 32 - 3
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| #* weight 64 - 1
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| # Reduction layer 2: this layer will be the last, because any weight has at most three input wires.
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| #* Weights 1, 2, 4, 64 pass through.
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| #* Add a full adder for weight 8, outputs: 1 weight-8 wire, 1 weight-16 wire
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| #* Add a half adder for weight 16, outputs: 1 weight-16 wire, 1 weight-32 wire<br>Weight 8's full adder has already produced one weight-16 output wire. By using a half adder for the two weight-16 input wires, the Dadda tree ensures that the last layer has only two output wires for any weight.
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| #* Add a full adder for weight 32, outputs: 1 weight-32 wire, 1 weight-64 wire
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| # Outputs:
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| #* weight 1 - 1
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| #* weight 2 - 2
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| #* weight 4 - 1
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| #* weight 8 - 1
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| #* weight 16 - 2
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| #* weight 32 - 2
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| #* weight 64 - 2
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| Compared to a Wallace tree, which requires ten full adders and half adders, the reduction phase of the Dadda multiplier has the same delay, but requires only six. On the other hand, the final adder has 6-bit inputs (weights 2 to 64), rather than 5-bit (weights 8 to 128) as in a Wallace tree.
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| ==See also==
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| * [[Booth's multiplication algorithm]]
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| * [[Fused multiply–add]]
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| * [[Wallace tree]]
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| * [[BKM algorithm]] for complex logarithms and exponentials
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| * [[Kochanski multiplication]] for [[modular arithmetic|modular]] multiplication
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| ==References==
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| * {{cite journal
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| | last = Dadda
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| | first = L.
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| | authorlink = Luigi Dadda
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| | title = Some schemes for parallel multipliers
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| | journal = Alta Frequenza
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| | volume = 34
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| | pages = 349–356
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| | year = 1965 }}
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| * {{cite conference
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| | last = Townsend
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| | first = W.
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| | coauthors = Swartzlander, E.; Abraham , J.
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| | title = A Comparison of Dadda and Wallace Multiplier Delays
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| | booktitle = SPIE Advanced Signal Processing Algorithms, Architectures, and Implementations XIII
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| | date = 2003-08-06
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| | url = http://www.cerc.utexas.edu/~whitney/pdfs/spie03.pdf }}
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| [[Category:Digital circuits]]
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| [[Category:Computer arithmetic]]
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