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| [[Image:C-element.svg|right|upright=0.2]]
| | Marvella is what you can call her but it's not the most feminine name out there. Years in the past he moved to North Dakota and his family enjoys it. One of the issues he loves most is ice skating but he is having difficulties to discover time for it. For many years I've been working as a payroll clerk.<br><br>my web-site - at home std testing ([http://vacabnb.com/index.php?do=/profile-473/info/ additional reading]) |
| The Muller '''C-element''', or Muller C-gate, is a commonly used [[asynchronous logic]] component originally designed by [[David E. Muller]]. It applies logical operations on the inputs and has [[hysteresis]]. The output of the C-element reflects the inputs when the states of all inputs match. The output then remains in this state until the inputs all transition to the other state. This model can be extended to the [[asymmetric C-element]] where some inputs only affect the operation in one of the transitions (positive or negative).
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| The Muller '''C-element''' was first used in the arithmetic logic unit (ALU) of the [[ILLIAC II]] supercomputer, proposed in 1958, and operational in 1962.
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| ==Implementations of the C-element==
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| Different implementations have been proposed, using CMOS transistors or other existing gates.
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| ===Semi-static===
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| [[Image:C_element_shaded2.svg|right]]
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| [[Image:CMOS-Muller-C-Gate-Implementation.svg|thumb|right|upright=1.5|A static 2-input Muller C-element. Note that transistors, branched in parallel, control the feedback signal.]]
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| [[Image:C-element-from-NANDs.svg|thumb|upright=1.5|A 2-input C-element using four NAND gates.]]
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| One of the most commonly used is the semi-static C-element, which stores its previous state with two cross-coupled inverters, similar to an [[Static random access memory|SRAM]] cell. One of the inverters is weaker than the rest of the circuit, so it can be overpowered by the [[CMOS|pull-up and pull-down networks]]. | |
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| If both inputs are 0, then the pull-up network changes the [[Latch (electronics)|latch]]'s state, and the C-element outputs a 0. If both inputs are 1, then the pull-down network changes the latch's state, making the C-element output a 1. Otherwise, the input of the latch is not connected to either V<sub>dd</sub> or ground, and so the weak inverter (drawn smaller in the diagram) dominates and the latch outputs its previous state.
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| ===Static===
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| In [[Static logic (digital logic)|static]] CMOS, a C-element can be designed that doesn't rely on the weak feedback inverter.
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| ===Gate-level implementations===
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| Different gate-level implementations are possible. They can be built from NAND gates or from [[RS_latch#Simple_set-reset_latches|RS latches]].
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| == Truth table ==
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| Here is the truth table for a 2-input c-gate. <math>Y_{n-1}</math> denotes a "no change" condition.
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| {| class="wikitable"
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| | A B || <math>Y</math>
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| |-
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| | 0 0 || 0
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| |-
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| | 0 1 || <math>Y_{n-1}</math>
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| |-
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| | 1 0 || <math>Y_{n-1}</math>
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| |-
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| | 1 1 || 1
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| |}
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| ==C-element based decoding method==
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| A C-element based implementation of iterative [[Low-density parity-check code|Low-density parity-check code (LDPC)]] decoders in logic technologies has been proposed by Tang ''et al.''<ref>{{Citation |first=Y. |last=Tang |first2=C. |last2=Winstead |first3=E. |last3=Boutillon |first4=C. |last4=Jégo |first5=M. |last5=Jézéquel |title=An LDPC decoding method for fault-tolerant digital logic |journal=Proc. Circuits and Systems (ISCAS), 2012 IEEE International Symposium on |date=May 2012 |pages=3025–3028 |doi= }}</ref> The technique employs cascaded C-elements and XORs to achieve efficient error-correction in the presence of internal upsets.
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| ==References==
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| {{Reflist|30em}}
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| *{{Citation |first=D. E. |last=Muller |first2=W. S. |last2=Bartky |title=A Theory of Asynchronous Circuits |journal=Proc. Int'l Symp. Theory of Switching, Part 1 |publisher=Harvard Univ. Press |year=1959 |pages=204–243 |doi= }}
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| * "Introduction to Speed-Independent Circuits," Session IV, Proc. 2nd Ann. Symp. Switching Circuit Theory and Logical Design, AIEE, 1961, pp. 85–110. Organized by David E. Muller, this session included four papers: R.E. Miller, "An Introduction to Speed Independent Circuit Theory"; R.E. Swartwout, "One Method for Designing Speed Independent Logic for Control"; J.E. Robertson, "Problems in the Physical Realization of Speed Independent Circuits"; and D.B. Gillies, "A Flowchart Notation for the Description of a Speed Independent Control."
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| *
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| ==External links==
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| * [http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/16-flipflops/70-cgate/muller-cgate3.html Muller C-Gate Simulation]
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| [[Category:Logic gates]]
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| [[Category:Digital electronics]]
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Marvella is what you can call her but it's not the most feminine name out there. Years in the past he moved to North Dakota and his family enjoys it. One of the issues he loves most is ice skating but he is having difficulties to discover time for it. For many years I've been working as a payroll clerk.
my web-site - at home std testing (additional reading)